module Pwm_Core
(
input clk,rst_n,
input [31:0] CCR0,
input [31:0] CCR1,
input en,
output pwm_out
);
reg [31:0] cnt;
always @(posedge clk,negedge rst_n)
begin 
	if(!rst_n) 
		cnt<=0;
	else if(cnt<CCR0)
		cnt<=cnt+1'b1;
	else 
		cnt<=0;
end 

assign pwm_out=en?(cnt<=CCR1?1:0):0;
endmodule 